The invention concerns a memory circuit that includes at least two areas each having a plurality of memory cells. The invention is preferably but not exclusively used for DRAMs (Dynamic Random Access Memories).
In data memories the binary memory cells are often grouped into several separate areas, each having its own group of read amplifiers, each of which is responsible for a subset of the cells of the area concerned. Normally the cells of each memory area form a matrix of rows and columns, and each column is assigned a read amplifier. Each row can be selectively addressed by enabling an assigned word line. This enabling action causes each cell of the row concerned to pass their memory contents to the read amplifier assigned to their column, which subsequently generates an amplified signal representing the binary value of the saved item of data. By closing a transfer switch assigned to the read amplifier, this binary representation is then transferred to a local data line, which can be connected via a line switch to a master data line in order to transfer the binary representation to a secondary read amplifier where it is amplified in order to output the item of data.
Generally the local data lines and the master data line have two conductors. For this plurality each primary read amplifier has a symmetrical output configuration. If it has sensed the contents of a memory cell to be an item of data corresponding to the first binary value, one output connection of the amplifier goes to a first defined logic potential, and the other output connection goes to a second defined logic potential. If the item of data contained in the cell corresponds to the second binary value, then the two logic potentials at the output terminals of the amplifier appear inverted. By closing the transfer switch when the line switch is closed, the output potentials of the read amplifier are applied to the conductors of the local data line, and reach the conductors of the master data line via the line switch to set up a potential difference there representing the sensed item of data. The secondary read amplifier is therefore configured as a differential amplifier with symmetrical input. Conventionally, the supply potentials at the base side and load side of this amplifier lie symmetrically about the center of the two logic potentials, and close to one or the other logic potential respectively.
Before closing a line switch and before a transfer switch to any of the primary read amplifiers is closed, the conductors of the local data line concerned are equalized to a certain potential that normally lies in the center of the two logic potentials. Before closing a line switch, the conductors of the master data line are also equalized to a certain potential. It is conventional to choose one of the two logic potentials for this second equalization potential, and specifically a potential that is equal or nearly equal to the load-side supply potential of the secondary read amplifier. This amplifier then remains in the linear region of the amplifier characteristic when the input terminals are driven by the potential difference that is set up on the conductors of the master data line after closing the line switch and opening a transfer switch.
When the line switch is closed, which normally happens before the transfer switch is closed, both conductors of the local data line go initially to the equalization potential of the master data line. For this to happen the source of this equalization potential must supply current. If then, after isolating this potential source from the conductors of the master data line, the transfer switch is closed, the primary read amplifier must supply current to drag one of the conductors from both the local data line and the master data line away from the equalization potential.
It is accordingly an object of the invention to provide a memory circuit which overcomes the above-mentioned disadvantages of the heretofore-known memory circuits of this general type and which has a reduced current consumption.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory circuit, including:
at least two memory areas each including a plurality of cells for storing in each case an item of binary data;
a two-conductor local data line assigned to a corresponding one of the at least two memory areas, the two-conductor local data line including a first conductor and a second conductor;
selectively closable transfer switches;
each of the at least two memory areas including a plurality of primary read amplifiers each assigned to a respective subset of the cells in order to sense an item of binary data saved in an addressed one of the cells of the subset;
the primary read amplifiers setting, via respective ones of the selectively closable transfer switches, the first conductor of the two-conductor local data line to a first logic potential and the second conductor of the two-conductor local data line to a second logic potential, if the item of binary data having been sensed has a first binary value, and setting the first conductor to the second logic potential and the second conductor to the first logic potential, if the item of binary data having been sensed has a second binary value;
a selectively controllable line switch;
a secondary read amplifier configured as a differential amplifier and having input terminals;
a two-conductor master data line including two conductors respectively connected to the input terminals of the secondary read amplifier;
the first conductor and the second conductor of the two-conductor local data line being connected, via the selectively controllable line switch, to the conductors of the two-conductor master data line;
precharging devices for equalizing, prior to closing a respective one of the selectively closable transfer switches, the first conductor and the second conductor of the two-conductor local data line to a potential lying between the first logic potential and the second logic potential, and for equalizing, prior to closing the selectively controllable line switch, the two conductors of the master data line to a potential lying between the first logic potential and the second logic potential; and
the secondary read amplifier having an amplifying operating range and being provided with supply potentials such that the secondary read amplifier operates within the amplifying operating range when either one of the input terminals of the secondary read amplifier is driven to the first logic potential and another one of the input terminals of the secondary read amplifier is driven to the second logic potential.
In other words, the invention is realized in a memory circuit having at least two areas, each of which contains a plurality of cells for storing in each case an item of binary data, and a plurality of primary read amplifiers, each of which is assigned to a subset of these cells in order to sense the item of data saved in one addressed member of the assigned cells, and, via a selectively closable transfer switch, to set the first conductor of a two-conductor local data line assigned to the corresponding memory area to a first logic potential, and the second conductor of this data line to a second logic potential, if the sensed item of data has the first binary value, and the first conductor to the second logic potential, and the second conductor to the first logic potential, if the sensed item of data has the second binary value, the conductors of each local data line being connected via an assigned, selectively controllable line switch to the conductors of a two-conductor master data line that is connected to the input terminals of a secondary read amplifier configured as a differential amplifier, and precharging devices being provided in order to equalize both conductors of the assigned local data line, prior to the closure of the transfer switch of a primary read amplifier, to a potential lying between the first and the second logic potential, and to equalize the potentials of both conductors of the master data line prior to the closure of a line switch. According to the invention the equalization potential for the master data line also lies between the first and the second logic potential, and the supply potentials of the secondary read amplifier are provided so that it remains within the amplifying operating range when either of its input terminals is being driven to the first logic potential and the other input terminal is being driven to the second logic potential respectively.
Due to to the invention the current consumption from the source of the equalization potential for the master data line and the current consumption via the primary read amplifier is less than in customary practice. The smaller the difference between the equalization potentials of the local and master data line, and the closer these equalization potentials lie to the center point between the two logic levels, the lower the current consumption; it is minimized when the equalization potential to which the master data line is precharged is equal to the value lying in the center of the two logic potentials, i.e. is an average value of the two logic potentials. A further advantage of the invention is that the second amplifier has a larger input control range and is therefore less sensitive to noise.
According to another feature of the invention, the precharging devices respectively provide a first equalization potential for the two-conductor master data line and a second equalization potential for the two-conductor local data line such that the first equalization potential is equal to the second equalization potential.
According to yet another feature of the invention, the precharging devices respectively provide an equalization potential for the two-conductor master data line and for the two-conductor local data line such that the equalization potential is equal to a center value between the first logic potential and the second logic potential.
According to a further feature of the invention, the secondary read amplifier is provided with the supply potentials such that the amplifying operating range of the secondary read amplifier lies symmetrically about the center value between the first logic potential and the second logic potential.
According to another feature of the invention, the secondary read amplifier is provided with a base-side supply potential and a load-side supply potential as the supply potentials such that the base-side supply potential lies further away from a center value between the first and second logic potentials than the load-side supply potential.
According to another feature of the invention, a bit line leads to an assigned one of the primary read amplifiers; the cells are memory cells each including a capacitor as a memory element and a field-effect transistor as a select switch; the field-effect transistor being controllable for selectively connecting the capacitor to the bit line; the secondary read amplifier being provided with a base-side supply potential as one of the supply potentials; and the field-effect transistor having a substrate provided with the base-side supply potential for minimizing leakage currents when the field-effect transistor is in a blocking state.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory circuit having a plurality of memory areas, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.